Senior Mask Layout Design Engineer
NVIDIA
Taipei
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Interpersonal skills","Problem-solving","Attention to detail"]Senior Mask Layout Design Engineer to perform physical layout for high-speed mixed-signal circuits (PLL, memory I/O, SerDes, ESD) in sub-micron CMOS FinFET tech using Cadence; collaborate with ASIC/mixed-signal teams to tailor designs for VLSI products, including floorplanning and layout verification against rules and schematics.

