Senior CPU RTL Design Engineer – Power Management
Intel
Austin, Phoenix
Workplace: HybridFull timeUSD 164,470 - 269,100 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 9+ yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","DVFS","Power management","Multi-clock domain","CDC","X86 assembly","Static timing analysis","Lint","UPF"]Senior CPU RTL Design Engineer focusing on power-aware, low-power CPU/SoC RTL design. Work with architecture, verification and physical teams to implement DVFS, power/thermal management, and PPA optimization across multi-clock domains for high-performance, power-efficient processors in a collaborative, fast-moving environment.
