Senior Signal Integrity Engineer – LPU Packaging

NVIDIA
United States
Workplace: HybridFull timeUSD 168,000 - 264,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Signal integrity","High-speed interconnect","SerDes","EM","PAM4","NRZ","Channel modeling","S-parameters","IBIS-AMI","Lab measurements","VNA","TDR","Oscilloscope","Automation","Flow development"]

Lead high-speed SerDes signal integrity design across die, package, board, and interconnects; develop SI simulation for 2.5D/3D packaging; build co-simulation methodologies for HPC/data center systems; model and optimize package escapes and interconnects; correlate simulations with lab measurements to ensure electrical performance targets and enable reusable SI flows.

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FursaFursa
NVIDIA
NVIDIA
2 months ago

Senior Signal Integrity Engineer – LPU Packaging

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Lead high-speed SerDes signal integrity design across die, package, board, and interconnects; develop SI simulation for 2.5D/3D packaging; build co-simulation methodologies for HPC/data center systems; model and optimize package escapes and interconnects; correlate simulations with lab measurements to ensure electrical performance targets and enable reusable SI flows.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces.
  • •Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with strong focus on channel loss, discontinuities, return path behavior, and crosstalk.
  • •Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems.
  • •Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures.
  • •Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met.

Pay and Benefits

Salary: USD 168,000 - 264,500 annually
Equity and Bonus:Equity
Perks:Equity

Key Requirements

  • •8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles.
  • •BS, MS, or PhD in Electrical Engineering or equivalent experience
  • •Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior
  • •Proven experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale system applications
  • •Hands-on experience with industry-standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent
Experience:8+ yearsData centerHPCAISemiconductors
Education:Bachelor's
Skills:Signal integrityHigh-speed interconnectSerDesEMPAM4NRZChannel modelingS-parametersIBIS-AMILab measurementsVNATDROscilloscopeAutomationFlow development
Tech Stack:Ansys HFSSSIwaveCadence SigrityADSHSPICEVNATDROscilloscope

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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