Padring Verification Engineer
Taiwan
Workplace: OnsiteFull timeFunction: QA, Test & Release EngineeringExperience: 1-8 yearsEducation: mastersSkills: ["Analytical","Problem-solving","Communication","Cross-functional collaboration"]Develop and maintain scalable padring verification methodologies, infrastructure, and automation for RTL integration, connectivity verification, and chip assembly. Execute padring verification and connectivity signoff for GPU and Tegra projects by analyzing results, debugging failures, and driving issues to closure. Verify DFT-related padring logic (boundary scan and test-access connectivity), define verification plans with assertions/checkers/coverage/regressions, and build tools/flows to catch integration issues early while collaborating across RTL, DFT, Physical Design, CAD, Package Design, and Software teams.
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