RTL Design Manager

AMD
San Jose
Workplace: HybridFull timeUSD 163,100 - 279,600 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Problem-solving","Detail-oriented","Analytic","Self-starter"]

Lead a small front-end RTL design and integration team within the AECG IP & SOC group, driving first-pass silicon success. Own block design and implementation across functional, timing, area, and power requirements, guide verification, and implement logic for efficient test and debug. Collaborate with architecture, IP, physical design, and product engineers while adding automation to improve design efficiency and translating complex issues for both executives and technical teams.

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FursaFursa
AMD
AMD
1 day ago

RTL Design Manager

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 41 minutes agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Lead a small front-end RTL design and integration team within the AECG IP & SOC group, driving first-pass silicon success. Own block design and implementation across functional, timing, area, and power requirements, guide verification, and implement logic for efficient test and debug. Collaborate with architecture, IP, physical design, and product engineers while adding automation to improve design efficiency and translating complex issues for both executives and technical teams.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead a small, high-performance engineering team.
  • •Own the design and implementation of blocks to meet functional, timing, area and power requirements.
  • •Guide and review verification for the blocks.
  • •Design and implement logic functions that enable efficient test and debug.
  • •Implement automation to increase design team efficiency.

Pay and Benefits

Salary: USD 163,100 - 279,600 annually

Key Requirements

  • •Own the design and implementation of blocks meeting functional, timing, area, and power requirements.
  • •Strong front-end RTL engineering background with experience in design integration at the SoC level.
  • •Experience with Arm architecture and APB, AXI, and CHI protocols.
  • •Experience with design reuse (RTL, constraints, and waivers) and timing constraints/exceptions.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationProblem-solvingDetail-orientedAnalyticSelf-starter
Tech Stack:RTLArmAPBAXICHISoCPERLPythonTclTiming constraintsTiming exceptionsLINTCDCUPF

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn