ASIC DFT Technical Leader

Cisco
San Jose
Workplace: HybridFull timeUSD 214,100 - 309,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Leadership","Collaboration"]

Lead Design-for-Test (DFT) activities for next-generation networking ASICs in the Silicon One development organization. Partner with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early. Own the DFT and quality process across the implementation flow and post-silicon validation, including exposure to physical design signoff. Help craft and validate DFT patterns from first silicon through production.

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FursaFursa
Cisco
Cisco
5 days ago

ASIC DFT Technical Leader

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Last checked: 5 hours agoStatus: Live

Job Summary

Lead Design-for-Test (DFT) activities for next-generation networking ASICs in the Silicon One development organization. Partner with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early. Own the DFT and quality process across the implementation flow and post-silicon validation, including exposure to physical design signoff. Help craft and validate DFT patterns from first silicon through production.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive DFT requirements early by working with front-end RTL and backend physical design teams to understand chip architecture.
  • •Lead the DFT and quality process across the full implementation flow and into post-silicon validation.
  • •Support post-silicon validation using DFT patterns and guide debugging from first silicon to production.
  • •Collaborate on physical design signoff activities with additional exposure to signoff processes.
  • •Contribute to crafting next-generation networking ASICs by applying DFT methodologies and verification approaches.

Pay and Benefits

Salary: USD 214,100 - 309,800 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalDisability CoverageLife InsuranceRsus

Key Requirements

  • •Bachelor's or Master's degree in Electrical or Computer Engineering with at least 12+ years of experience.
  • •Experience in post-silicon debug from first silicon to production.
  • •Experience with JTAG protocols plus Scan and BIST architectures, including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • •Experience with gate-level simulation and debugging using VCS and other simulators.
Experience:12+ years
Education:Bachelor's in Electrical or Computer Engineering
Skills:LeadershipCollaboration
Tech Stack:DFTRTLPhysical designJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeVCSGate-level simulationVerilogSystemVerilogFunctional verificationDFT patternsTest static timing analysis

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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