PD Layout expert
Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: OtherExperience: 5+ yearsEducation: bachelorsSkills: []Own physical design execution for SoCs in high-growth MCU domains, focusing on floorplanning, congestion and DRC analysis, and layout closure. Drive power-grid and IR drop validation for balanced utilization, collaborate with timing/ATD/ESD and physical verification teams to protect design intent, and lead ECO implementation for DRC/LVS fixes. Use advanced EDA workflows (e.g., Innovus) and automation scripting (TCL/Perl/Python) to enable correct-by-construction flows and explore AI/ML-assisted improvements.

