SoC Verification Engineer – NoC / UVM
AMD
San Jose
Workplace: HybridFull timeFunction: Software EngineeringEducation: bachelorsSkills: ["SystemVerilog","UVM","SVA","Verilog","Constraint-random","Coverage-driven","Formal verification"]Verification engineer responsible for leading and contributing to the verification of Network-on-Chip IPs and subsystems. You will architect and develop simulation/formal verification environments (SystemVerilog/UVM), create testbenches, drive verification closure, and collaborate with architecture and design teams on NoC/SoC verification.
