Lead Design Engineer ( Synthesis/LEC/CLP )

Cadence Design Systems
Bengaluru, Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5-8 yearsEducation: bachelorsSkills: ["Communication skills","Independent problem-solving","Issue triage","Technical documentation","Collaboration"]

Lead execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. Independently debug synthesis and LEC issues, investigate NEQs and constraint mismatches, and contribute to CLP sign-off. Improve QoR through Genus synthesis runs, write and maintain ECO scripts and timing/power constraints, and triage/document issues for complex escalations while collaborating with PD, DFT, and RTL teams.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Lead Design Engineer ( Synthesis/LEC/CLP )

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Lead execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. Independently debug synthesis and LEC issues, investigate NEQs and constraint mismatches, and contribute to CLP sign-off. Improve QoR through Genus synthesis runs, write and maintain ECO scripts and timing/power constraints, and triage/document issues for complex escalations while collaborating with PD, DFT, and RTL teams.
Location: Bengaluru, Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs.
  • •Run and debug LEC sign-off on design blocks; investigate and resolve NEQs and constraint mismatches.
  • •Improve QoR using Genus synthesis runs and debug SDC/constraint issues.
  • •Support CLP flows and contribute to CLP sign-off through execution and issue resolution.
  • •Write and maintain ECO scripts and timing/power constraints, independently triage/document issues, and escalate complex/systemic problems as needed.

Key Requirements

  • •5–8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows
  • •Working knowledge of Cadence Genus and Conformal (LEC and/or CLP)
  • •Familiarity with UPF/CPF-based power intent (IEEE 1801)
  • •Scripting proficiency in Tcl, Perl, or Python in Unix/Linux environments
  • •Solid digital design fundamentals, STA basics, and low-power architecture concepts
Experience:5-8 yearsASIC designSoCLow-power verificationEDAPower intentRTL/DFT collaboration
Education:Bachelor's in Electrical/Electronic
Skills:Communication skillsIndependent problem-solvingIssue triageTechnical documentationCollaboration
Tech Stack:ASICSoCSynthesisLECCLPUPFCPFIEEE 1801GenusConformalECO scriptsSDCTclPerlPythonUnixLinuxSTA

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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