Sr Principal Verification Engineer
Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 5-7 yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","C++","Cadence","HDL","HVL","Verilog-A","Emulation"]Lead development and execution of UVM-based verification environments for memory IP models (SDRAM, UFS, MPHY, DFI PHY) in a hardware verification context. Design, analyze requirements, integrate toolchains, and mentor engineers across functions to ensure high-quality SoC verification. Deep expertise in Verilog/SystemVerilog, HDL/HVL, and Cadence tools, with cross-geography collaboration.
