DFT Implementation Engineer

Intel
United States
Workplace: OnsiteFull timeUSD 141,910 - 200,340 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Cross-functional collaboration"]

Develop and implement Design for Test (DFT) logic for Intel SoC and IP designs, including SCAN, MBIST, and BSCAN features. Support timing closure and generate manufacturing test content for rapid HVM bring-up on automatic test equipment (ATE). Collaborate across architecture, design, verification, and manufacturing teams to define DFT specifications, integrate RTL/structural code, verify on silicon, and drive high test coverage to meet DPM and quality goals.

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FursaFursa
Intel
Intel
1 month ago

DFT Implementation Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Develop and implement Design for Test (DFT) logic for Intel SoC and IP designs, including SCAN, MBIST, and BSCAN features. Support timing closure and generate manufacturing test content for rapid HVM bring-up on automatic test equipment (ATE). Collaborate across architecture, design, verification, and manufacturing teams to define DFT specifications, integrate RTL/structural code, verify on silicon, and drive high test coverage to meet DPM and quality goals.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop logic design and RTL coding to support DFT features such as SCAN, MBIST, and BSCAN.
  • •Provide timing closure support and generate test content for manufacturing.
  • •Collaborate in defining DFT architecture and microarchitecture features for blocks, subsystems, and SoCs.
  • •Write, integrate, and verify RTL and structural code for DFT functionality, and drive verification to achieve specifications.
  • •Develop HVM content for bring-up and production on ATE, and work with post-silicon and manufacturing teams to verify features and document learnings.

Pay and Benefits

Salary: USD 141,910 - 200,340 annually
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •5+ years of experience in DFT, SoC design, or related semiconductor design areas.
  • •Hands-on experience with ATPG, scan insertion, and/or MBIST/repair.
  • •RTL design experience using Verilog, VHDL, or SystemVerilog.
  • •Experience with Tessent Shell flows and SSN methodology.
Experience:5+ yearsSemiconductorsSoC designASIC designDFT
Education:Bachelor's in Electrical Engineering, Computer Engineering, or a related field
Skills:Cross-functional collaboration
Tech Stack:DFTSCANMBISTBSCANRTLVerilogVHDLSystemVerilogATPGScan insertionTessent ShellSSN methodologyTessent Fast IOISTKIEEE 1687 (IJTAG)IEEE 1149.1 (JTAG)IEEE 1500 (Core Test)IEEE 1838Siemens EDA (Mentor) TessentSynopsys DFT Compiler

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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Glassdoor: 3.8
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