Sr. Design Verification Engineer

AMD
Santa Clara, Austin
Workplace: HybridFull timeUSD 124,040 - 212,640 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Ownership","Technical leadership","Problem-solving","Debugging","Communication"]

Own verification for complex, high-performance ASIC designs for next-generation data center networking products. Build UVM-based testbench architectures across IP, subsystem, and SoC levels, define test plans and coverage strategy, and develop SystemVerilog verification components. Execute regressions, debug architectural/functional/performance issues, and drive verification sign-off. Collaborate with RTL, architecture, validation, firmware, and emulation teams, and mentor junior verification engineers while improving methodology and automation.

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FursaFursa
AMD
AMD
16 hours ago

Sr. Design Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Own verification for complex, high-performance ASIC designs for next-generation data center networking products. Build UVM-based testbench architectures across IP, subsystem, and SoC levels, define test plans and coverage strategy, and develop SystemVerilog verification components. Execute regressions, debug architectural/functional/performance issues, and drive verification sign-off. Collaborate with RTL, architecture, validation, firmware, and emulation teams, and mentor junior verification engineers while improving methodology and automation.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
  • •Drive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.
  • •Develop SystemVerilog components such as stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
  • •Own execution of verification plans, regression triage, and debug of architectural/functional/performance issues, including root-causing failures across RTL and interfaces.
  • •Collaborate cross-functionally with RTL, architecture, validation, firmware, and emulation/HAPS teams, and mentor junior engineers.

Pay and Benefits

Salary: USD 124,040 - 212,640 annually

Key Requirements

  • •Expert-level knowledge of SystemVerilog and UVM
  • •Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
  • •Proven experience verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies
  • •Strong debug skills across architecture, RTL, and testbench layers
  • •Experience with data-path protocols such as PCIe, AXI, Ethernet, DDR, or DMA engines
Experience:ASICNetworkingData center
Education:Bachelor's in Electrical/Computer Engineering
Skills:OwnershipTechnical leadershipProblem-solvingDebuggingCommunication
Languages:En-us
Tech Stack:SystemVerilogUVMVCSVerdiDVEPythonPerlShellTclMakePCIeAXIEthernetDDRDMAUPFFormal verificationFPGAHAPSC/C++

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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