Texas Instruments

3 months ago

Digital Mixed Signal DV Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Own digital design verification for chip top levels by driving verification strategy, creating test plans, and building UVM-based testbenches. Execute RTL and gate-level simulations, run regressions, and track functional and code coverage to achieve 100% closure. Debug complex design and testbench issues, support post-silicon characterization with ATE pattern generation, and collaborate with architecture, design, and firmware teams to ensure successful product execution.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: QA, Test & Release Engineering

Seniority: Mid level

Key Responsibilities

•Drive the verification strategy, create test plans, and develop testbenches for chip top levels.
•Develop the DV environment from the ground up, coding UVM components such as agents, drivers, monitors, and scoreboards.
•Execute RTL and gate-level simulations, run regressions, and track functional and code coverage (Block, Expression, Toggle, FSM) to achieve full closure.
•Debug complex design and testbench issues using strong problem-solving skills.
•Support post-silicon activities by interacting with product and application engineering teams for ATE functional pattern generation and silicon characterization.

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering.
•Minimum 3 years of experience in IP-level and SoC-level Digital Design Verification.
•Strong expertise in SystemVerilog (SV) and UVM methodologies.
•Proficiency with Cadence simulation tools and environments (e.g., Xcelium, Vmanager).
•Effective communication and interpersonal skills to interact with worldwide cross-functional experts and stakeholders.

Experience:3-6 years

Education:Bachelor's

Skills:CommunicationInterpersonal skillsDebuggingProblem-solvingCross-functional collaboration

Tech Stack:SystemVerilog (SV)UVMCadenceXceliumVmanagerRTLGate Level Simulations (GLS)RegressionsFunctional coverageCode coverageI2CASISPIUARTPythonPerlShellFormal property verification (FPV)Connectivity checksUnreachability (UNR)

Company Brief

Texas Instruments

Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn

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Texas Instruments

3 months ago

Digital Mixed Signal DV Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: QA, Test & Release Engineering

Seniority: Mid level

Key Responsibilities

•Drive the verification strategy, create test plans, and develop testbenches for chip top levels.
•Develop the DV environment from the ground up, coding UVM components such as agents, drivers, monitors, and scoreboards.
•Execute RTL and gate-level simulations, run regressions, and track functional and code coverage (Block, Expression, Toggle, FSM) to achieve full closure.
•Debug complex design and testbench issues using strong problem-solving skills.
•Support post-silicon activities by interacting with product and application engineering teams for ATE functional pattern generation and silicon characterization.

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering.
•Minimum 3 years of experience in IP-level and SoC-level Digital Design Verification.
•Strong expertise in SystemVerilog (SV) and UVM methodologies.
•Proficiency with Cadence simulation tools and environments (e.g., Xcelium, Vmanager).
•Effective communication and interpersonal skills to interact with worldwide cross-functional experts and stakeholders.

Experience:3-6 years

Education:Bachelor's

Skills:CommunicationInterpersonal skillsDebuggingProblem-solvingCross-functional collaboration

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn