NVIDIA

3 months ago

Senior Package Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Senior IC Packaging Design Engineer responsible for high-speed interconnect layouts for ASIC packages in NVIDIA's IC Packaging team. Collaborates with SI/PI/HW and product teams to deliver PDN designs, develop substrate routing, and optimize pinout while driving reliability, productivity, and schedule adherence for Supercomputers and Datacenters.

Location: Israel

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Collaborate with the IC Packaging design team to implement high-speed PDN design for ASIC packages.
•Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, and power distribution using Cadence APD (Allegro) or SiP tools.
•Optimize package pinout incorporating system-level trade-offs of pins assignment.
•Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
•In close cooperation with the SI/PI/HW design teams and product teams; plan, manage stakeholders, and lead projects from start to finish.

Key Requirements

•B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience.
•5+ years hands-on in Package/PCB Layout and high-speed design signal integrity practices.
•Experience in substrate layout of wire bond and flip chip packages, preferred
•Knowledge in substrates or board manufacturing process
•Significant background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools

Experience:5+ yearsSemiconductorIC packagingHigh-speed electronics

Education:Bachelor's

Skills:Cadence APD (Allegro)Cadence VirtuosoSiPAPDPCB layoutSignal integritySubstrate layoutWire bondFlip chipCadence SigrityPowerSIAnsys SIwaveHFSSSkill languagePythonPerlShell scripting

Tech Stack:Cadence APDAllegroCadence VirtuosoSiPAnsys SIwaveHFSSSigrityPowerSIPythonPerlShell scripting

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

3 months ago

Senior Package Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Israel

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Collaborate with the IC Packaging design team to implement high-speed PDN design for ASIC packages.
•Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, and power distribution using Cadence APD (Allegro) or SiP tools.
•Optimize package pinout incorporating system-level trade-offs of pins assignment.
•Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
•In close cooperation with the SI/PI/HW design teams and product teams; plan, manage stakeholders, and lead projects from start to finish.

Key Requirements

•B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience.
•5+ years hands-on in Package/PCB Layout and high-speed design signal integrity practices.
•Experience in substrate layout of wire bond and flip chip packages, preferred
•Knowledge in substrates or board manufacturing process
•Significant background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools

Experience:5+ yearsSemiconductorIC packagingHigh-speed electronics

Education:Bachelor's

Skills:Cadence APD (Allegro)Cadence VirtuosoSiPAPDPCB layoutSignal integritySubstrate layoutWire bondFlip chipCadence SigrityPowerSIAnsys SIwaveHFSSSkill languagePythonPerlShell scripting

Tech Stack:Cadence APDAllegroCadence VirtuosoSiPAnsys SIwaveHFSSSigrityPowerSIPythonPerlShell scripting

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor