Design Verification Engineer
Anywhere
Full timeFunction: Design (Product/UX/UI/Visual)Experience: 3-8 yearsEducation: bachelorsSkills: ["SV-UVM","Formal verification","Python","Perl"]Design Verification Engineer at SSIR focuses on IP/Sub-system verification for High Speed Interfaces, Memory Technologies, and security features. You’ll design reusable DV components, use SV-UVM and formal methods, track coverage metrics, and work with protocols like PCIe, AMBA, and LPDDR, contributing to Samsung’s cutting-edge Foundry IP Digital Development.

