Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group

Micron Technology
Tokyo
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Technical leadership","Debugging","Root-cause analysis","Clear communication","Mentoring"]

Own and evolve timing-critical NAND datapath circuitry between the NAND array and page buffer within Micron’s NVEG organization. Drive datapath architecture for multi-plane, high-parallelism operation, define and analyze clock/data timing schemes, and lead timing adjustment, skew management, and layout-aware circuit design. Partner across page buffer, array device, physical design, test, and product teams, performing SPICE/Fast-SPICE (PVT/aging/Monte Carlo) simulation, silicon correlation, and margin/yield root-cause analysis.

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Micron Technology
Micron Technology
2 weeks ago

Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group

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Job Summary

Own and evolve timing-critical NAND datapath circuitry between the NAND array and page buffer within Micron’s NVEG organization. Drive datapath architecture for multi-plane, high-parallelism operation, define and analyze clock/data timing schemes, and lead timing adjustment, skew management, and layout-aware circuit design. Partner across page buffer, array device, physical design, test, and product teams, performing SPICE/Fast-SPICE (PVT/aging/Monte Carlo) simulation, silicon correlation, and margin/yield root-cause analysis.
Location: Tokyo
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own and evolve internal NAND datapath circuits, including array redundancy, wave pipeline/pulse-based datapath architecture, and data line sensing circuits.
  • •Define and analyze scalable datapath architecture supporting multi-plane and high-parallelism operation.
  • •Lead clock/data timing scheme definition for long interconnects and large-array topologies, including timing adjustment and skew management.
  • •Drive layout-aware circuit design and timing closure with parasitic-aware sizing, matching/symmetry, shielding/guarding, and practical route fixes with layout partners.
  • •Run SPICE/Fast-SPICE simulations across PVT/aging/variability (Monte Carlo), correlate silicon behavior to simulation, and perform margin/yield root-cause analysis while mentoring others and producing reusable design collateral.

Key Requirements

  • •BS or MS in Electrical Engineering with 8+ years of relevant experience.
  • •Experience in physical design flows and optimization; proven ownership from concept to design, layout, signoff, and silicon correlation.
  • •Deep expertise in CMOS analog/mixed-signal circuit design and device physics fundamentals.
  • •High-speed datapath timing analysis experience, including wave-pipelined/pulse-based timing.
  • •Strong simulation and debug skills using SPICE/Fast-SPICE with corner/Monte Carlo analysis and failure-mode thinking.
Experience:8+ yearsSemiconductorsMemoryNANDDRAM
Education:Bachelor's in Electrical Engineering
Skills:Technical leadershipDebuggingRoot-cause analysisClear communicationMentoring
Tech Stack:CMOSAnalog/mixed-signalSPICEFast-SPICEPVTMonte CarloDDR4DDR5LPDDR5LPDDR6HBM3HBM3EHBM4

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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