Etched

4 months ago

DFT (Design For Test) Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Design For Testability (DFT) Engineer to ensure robust testability of ICs from design through production. Lead DFT architecture for ASIC/SoC, implement standard DFT methodologies, collaborate with design/verification teams, and drive verification, production test, and documentation to improve coverage, yield, and reliability in a high-performance silicon environment.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Develop and implement robust DFT architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
•Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
•Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle; analyze test results and silicon debug data to drive improvements in coverage, yield, and reliability.
•Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features; apply simulation-based and formal verification techniques.
•Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production and generate production-quality test patterns.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVisionRelocationHousing SubsidyWellness StipendMeal Allowance

Key Requirements

•10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
•Proficiency in SystemVerilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
•Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.
•Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues.
•A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).

Experience:SemiconductorsASICSoCHardware

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solving

Tech Stack:SystemVerilogSynopsys DFT CompilerCadence Encounter TestMentor TessentPythonPerlTCL

Company Brief

Etched

Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor

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Etched

4 months ago

DFT (Design For Test) Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Develop and implement robust DFT architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
•Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
•Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle; analyze test results and silicon debug data to drive improvements in coverage, yield, and reliability.
•Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features; apply simulation-based and formal verification techniques.
•Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production and generate production-quality test patterns.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVisionRelocationHousing SubsidyWellness StipendMeal Allowance

Key Requirements

•10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
•Proficiency in SystemVerilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
•Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.
•Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues.
•A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).

Experience:SemiconductorsASICSoCHardware

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solving

Tech Stack:SystemVerilogSynopsys DFT CompilerCadence Encounter TestMentor TessentPythonPerlTCL

Company Brief

Etched

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor