Senior FPGA Verification Engineer, Air Dominance and Strike

Anduril
United States
Workplace: OnsiteFull timeUSD 166,000 - 220,000Function: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Teamwork","Debugging"]

Own FPGA/SoC verification for flight-critical avionics running on AMD (Xilinx) platforms. Build UVM-based verification environments with coverage-driven planning, constrained-random test sequences, functional coverage, and regression suites. Write SystemVerilog Assertions, analyze code coverage to closure, and debug failures using waveform tools and simulation logs. Ensure verification meets DO-254 and related safety standards while partnering with design teams on RTL reviews and board bring-up.

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Anduril
Anduril
6 days ago

Senior FPGA Verification Engineer, Air Dominance and Strike

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Own FPGA/SoC verification for flight-critical avionics running on AMD (Xilinx) platforms. Build UVM-based verification environments with coverage-driven planning, constrained-random test sequences, functional coverage, and regression suites. Write SystemVerilog Assertions, analyze code coverage to closure, and debug failures using waveform tools and simulation logs. Ensure verification meets DO-254 and related safety standards while partnering with design teams on RTL reviews and board bring-up.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Architect and implement UVM verification environments for AMD (Xilinx) FPGA/SoC designs, including drivers, monitors, predictors, and scoreboards.
  • •Develop verification plans with traceability to system and hardware requirements.
  • •Author SystemVerilog Assertions and build coverage models, driving functional coverage and code coverage to closure.
  • •Create constrained-random and transaction-level test sequences; establish regression suites and track coverage metrics and verification progress.
  • •Debug failures using waveform tools and simulation logs, collaborate with design engineers on RTL reviews and bug resolution, and support hardware validation/board bring-up while meeting DO-254 safety standards.

Pay and Benefits

Salary: USD 166,000 - 220,000
Equity and Bonus:Equity

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •8+ years of experience in FPGA/ASIC verification.
  • •Proficiency in SystemVerilog, UVM methodology, and SVA, including extending UVM testbenches.
  • •Experience with industry simulators such as Questa, VCS, Xcelium, or Vivado and Git-based code review workflows.
  • •Eligible to obtain and hold a U.S. Secret security clearance.
Experience:FPGA/ASIC verificationAvionicsFlight-critical
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:CommunicationTeamworkDebugging
Tech Stack:FPGAASICSoCAMD (Xilinx)UVMSystemVerilogSVAUVM testbenchesQuestaVCSXceliumVivadoGitLinuxWaveform toolsSimulation logsDO-254PythonTclMakefile

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn