Senior FPGA/ASIC Verification Engineer

Lead and mentor FPGA verification engineers in the Hardware Platform Group, driving DV architecture, test planning, and coverage strategy through final sign-off. Develop robust test benches and constrained-random tests, ensuring high-quality, reliable FPGA/ASIC designs via advanced debugging. Advance verification methodologies such as UVM/VMM, collaborating with architects, logic designers, and software engineers to align on system requirements. Deliver next-generation high-performance networking hardware with first-pass success.