ASIC Design & Verification Engineer

Contribute to Cisco’s Silicon One Front-End Design team, covering the chip design lifecycle from specification review and micro-architecture to RTL design verification and signoff/validation. Build and implement a UVM-based verification environment, collaborate with design engineers to resolve bugs and drive coverage closure, and partner with firmware/lab teams to verify chip flows. Perform lab debug, root-cause analysis, and post-silicon validation to ensure successful silicon readiness.