ASIC DFT STA Engineer

Develop and validate timing constraints for ASIC test modes across block, sub-chip, and full-chip levels, ensuring correctness for endpoints with missing clocks and related timing scenarios. Collaborate with cross-functional teams to communicate complex timing data and help lead DFT and quality processes throughout implementation and post-silicon validation. Streamline STA workflows through methodologies, guidelines, and checklists, with possible involvement in CDC checks and SDC flow development.