ASIC DFT Engineer

Cisco
Bengaluru, Chennai, Hyderabad
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 7-11 yearsEducation: mastersSkills: ["Debugging","Problem-solving","Verbal communication","Working in a multifaceted environment","Crafting solutions"]

Build and implement Hardware Design-for-Test (DFT) features that enable ATE, in-system testing, debug, and diagnostics across Cisco silicon. Develop innovative DFT IP and help integrate testability into RTL for full-chip design integration. Partner with design and verification teams to enable test logic integration and validation through implementation and post-silicon flows, including new device models and test/debug strategy reuse.

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FursaFursa
Cisco
Cisco
3 days ago

ASIC DFT Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live

Job Summary

Build and implement Hardware Design-for-Test (DFT) features that enable ATE, in-system testing, debug, and diagnostics across Cisco silicon. Develop innovative DFT IP and help integrate testability into RTL for full-chip design integration. Partner with design and verification teams to enable test logic integration and validation through implementation and post-silicon flows, including new device models and test/debug strategy reuse.
Location: Bengaluru, Chennai, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Implement DFT features that support ATE, in-system test, debug, and diagnostics for ASIC designs.
  • •Develop innovative DFT IP and contribute to full-chip design integration of testability features coordinated in the RTL.
  • •Collaborate with design, design-verification, and PD teams to integrate and validate test logic across implementation and post-silicon flows.
  • •Contribute to reusable test and debug strategies for new silicon device models, bare die, and stacked die.
  • •Debug and craft solutions with minimal mentorship while supporting hardware DFT and physical design aspects.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering with 7-11 years of experience.
  • •Knowledge of DFT, test, and silicon engineering trends.
  • •Experience with JTAG protocols and Scan/BIST architectures, including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • •Verification experience including SystemVerilog logic equivalency checking and validating test timing; gate-level simulation and debugging with VCS and other simulators.
Experience:7-11 years
Education:Master's in Electrical or Computer Engineering
Skills:DebuggingProblem-solvingVerbal communicationWorking in a multifaceted environmentCrafting solutions
Tech Stack:Hardware Design-for-Test (DFT)ATEJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeSystemVerilogVCSGate-level simulationRTLP1687TclPythonPerl

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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