ASIC Design STA Engineer

AMD
San Jose
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Problem-solving","Teamwork","Organization"]

ASIC Design STA engineer responsible for building and verifying timing constraints for large SoCs with 300+ clock domains, leveraging SDC expertise, EDA tools, and TCL scripting to automate RTL quality metrics, pre-route checks, and QoR cleanup while collaborating with CAD for synthesis/STA workflows in a hybrid, multi-block semiconductor environment.

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FursaFursa
AMD
AMD
3 months ago

ASIC Design STA Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

ASIC Design STA engineer responsible for building and verifying timing constraints for large SoCs with 300+ clock domains, leveraging SDC expertise, EDA tools, and TCL scripting to automate RTL quality metrics, pre-route checks, and QoR cleanup while collaborating with CAD for synthesis/STA workflows in a hybrid, multi-block semiconductor environment.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop complex multi-mode / multi-corner timing constraints compatible for RTL and signoff
  • •Maintain RTL quality metrics in complex, hierarchical designs and automate the process for efficiency
  • •Implement pre-route timing checks and QoR cleanup to eliminate timing constraint issues and ensure a quality handoff for STA checks
  • •Collaborate with CAD on pre-production synthesis (Design Compiler) and STA (Primetime) workflows
  • •Apply SDC expertise, proficiency with EDA tools, and TCL scripting in both EDA environments and standalone Linux shells

Key Requirements

  • •SDC development and debugging experience for complex, hierarchical designs; automation of timing constraint processes
  • •Proficiency with EDA tools (Design Compiler, Primetime, Spyglass, Fishtail, etc.) and TCL scripting in Linux
  • •Front-end (RTL) and back-end (Synthesis & P&R) timing processes familiarity; RTL quality metrics and QoR improvements
  • •Ability to develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff
  • •Strong written and verbal communication, and structured, organized work habits
Experience:SemiconductorsASIC design
Education:Bachelor's in Computer Engineering / Electrical Engineering
Skills:CommunicationProblem-solvingTeamworkOrganization
Languages:English
Tech Stack:SDCDesign CompilerPrimetimeSpyglassTCLEDA tools

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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