Design Verification Engineering Lead - Silicon One
Cisco
San Jose
Workplace: OnsiteFull timeUSD 210,600 - 305,100 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","UVM","Perl","Python","C++","Linux","Veloce","Palladium","Zebu","HAPS","PCIe","Ethernet","RDMA","TCP","Fibre Channel","Jasper Gold"]Lead design verification for Cisco Silicon One data-center ASICs, architecting DV infrastructure, developing and executing comprehensive test plans, and ensuring robust verification and coverage. Collaborate with ASIC designers, architects, and software teams to guarantee seamless integration and optimal performance of Cisco hardware platforms.
