ASIC Design Verification Engineering Leader

Cisco
San Jose
Workplace: OnsiteFull timeUSD 214,100 - 309,800 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Technical leadership","Cross-functional collaboration","Debugging","Hands-on problem solving"]

Lead ASIC design verification for next-generation data center solutions at Cisco. Architect and build DV infrastructure across block, cluster, and top-level environments, driving elite functional coverage and quality for complex silicon. Partner with design, emulation, and software teams to debug firmware issues and take ownership during hands-on ASIC bring-up, ensuring seamless integration and optimal hardware platform performance.

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FursaFursa
Cisco
Cisco
3 months ago

ASIC Design Verification Engineering Leader

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 1 week ago

Job Summary

Lead ASIC design verification for next-generation data center solutions at Cisco. Architect and build DV infrastructure across block, cluster, and top-level environments, driving elite functional coverage and quality for complex silicon. Partner with design, emulation, and software teams to debug firmware issues and take ownership during hands-on ASIC bring-up, ensuring seamless integration and optimal hardware platform performance.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect and build DV infrastructure from scratch across block, cluster, and top-level verification environments.
  • •Drive functional coverage and quality for highly complex silicon designs.
  • •Collaborate with design, emulation, and software teams to debug critical firmware issues.
  • •Own hands-on ASIC bring-up and guide integration for optimal hardware platform performance.
  • •Lead verification for complete SoC/ASIC (where applicable).

Pay and Benefits

Salary: USD 214,100 - 309,800 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalDisability CoverageLife InsurancePaid HolidaysPaid Leave

Key Requirements

  • •Typically requires a Bachelors + 12 years, Masters + 8 years, or PhD + 5 years of related experience.
  • •Hands-on experience with Verilog, SystemVerilog, and UVM within the last 2–3 years.
  • •Experience using scripting languages such as Perl or Python.
  • •Experience with ASIC design and verification processes, debugging, methodology, and tools.
  • •Experience verifying blocks/clusters or full chip-level ASIC.
Experience:ASICSiliconData center
Education:Bachelor's
Skills:Technical leadershipCross-functional collaborationDebuggingHands-on problem solving
Tech Stack:ASICVerilogSystemVerilogUVMPerlPythonLinuxC/C++VelocePalladiumZebuHAPSFormal verificationJasper GoldIev/vc formalPCIeEthernetRDMATCPFiber Channel

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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