Staff Layout Engineer

AMD
Milan
Workplace: RemoteFull timeEUR 55,160 - 78,800 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: mastersSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving","Collaboration"]

Design and implement high-speed SerDes analog/mixed-signal circuit layouts for AMD CPU/GPU connectivity solutions. Own block-level physical implementation including floorplanning, power distribution, clock and signal routing, and transistor-level layout. Perform post-layout analysis, support integration at block/IP/chip level, and drive layout methodology and productivity improvements through automation (e.g., Pcells). Coordinate across teams in different sites/time zones.

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FursaFursa
AMD
AMD
2 days ago

Staff Layout Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Design and implement high-speed SerDes analog/mixed-signal circuit layouts for AMD CPU/GPU connectivity solutions. Own block-level physical implementation including floorplanning, power distribution, clock and signal routing, and transistor-level layout. Perform post-layout analysis, support integration at block/IP/chip level, and drive layout methodology and productivity improvements through automation (e.g., Pcells). Coordinate across teams in different sites/time zones.
Location: Milan
Workplace: Remote
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Create high-speed, high-performance SerDes analog/mixed-signal layouts aligned to project requirements and specifications.
  • •Execute block-level physical implementation including floorplanning, power distribution, clock and signal routing, and transistor-level layout.
  • •Analyze circuit performance after layout and participate in block/IP/chip integration activities.
  • •Estimate schedules and track/report progress and status.
  • •Help define layout methodology and drive productivity improvements such as Pcell development and automation; assess/correct layout quality issues and provide feedback to design teams.

Pay and Benefits

Salary: EUR 55,160 - 78,800 annually

Key Requirements

  • •Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.
  • •Strong analog and mixed-signal layout fundamentals, including IR/EM, capacitances, RC delay, and self-heating.
  • •Strong physical design verification skills (e.g., LVS/DRC/ERC/ANT/ESD).
  • •Experience with high-speed SerDes block and PLL layout in advanced Fin-FET processes (plus).
  • •Ability to use Cadence SKILL and scripting/programming tools (e.g., Perl, Python, Tcl) and collaborate with distributed teams.
Education:Master's in Computer Engineering/Electrical Engineering
Skills:CommunicationTeamworkAnalytical thinkingProblem-solvingCollaboration
Languages:En-us
Tech Stack:SerDesCMOSFin-FETCadence SKILLPerlPythonTclLVSDRCERCANTESDPCELLFloor-planningPower distribution networkClock routingSignal routingTransistor-level layoutIREM

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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