DFT Timing Lead

AMD
Bengaluru
Workplace: HybridFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Administration & Executive AssistanceExperience: 8-15 yearsEducation: mastersSkills: ["Debug","Scripting","Collaboration"]

Lead DFT timing work within the S3 SoC DFT team to ensure next-generation AMD SoCs meet quality goals. Develop full-chip DFT synthesis and DFT STA constraints, define SOC test timing methodology, and create STA constraint coverage for DFT modes including ScanShift, Atspeed, and MBIST. Partner with design and physical design teams to resolve constraint issues, validate timing constraints, and build automation scripts to improve the flow.

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FursaFursa
AMD
AMD
10 hours ago

DFT Timing Lead

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Lead DFT timing work within the S3 SoC DFT team to ensure next-generation AMD SoCs meet quality goals. Develop full-chip DFT synthesis and DFT STA constraints, define SOC test timing methodology, and create STA constraint coverage for DFT modes including ScanShift, Atspeed, and MBIST. Partner with design and physical design teams to resolve constraint issues, validate timing constraints, and build automation scripts to improve the flow.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Develop full-chip DFT synthesis and DFT STA constraints.
  • •Create STA constraint development for DFT modes including ScanShift, Atspeed, and MBIST.
  • •Set up DFT timing constraints and define the overall SoC test STA methodology.
  • •Work with the design team to clean up DFT-related constraint issues.
  • •Collaborate with the physical design team to generate and validate timing constraints, and maintain automation scripts as needed.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •B.E/B.Tech or M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT experience.
  • •Experience in DFT architecture for complex chips.
  • •Exposure to static timing analysis (STA) and timing closure.
  • •Proven experience handling DFT constraints, including block and top-level test mode STA.
  • •Hands-on debug and scripting skills; familiarity with RTL quality check tools/methodologies such as Spyglass, CDC, and Lint.
Experience:8-15 yearsSemiconductorSoCDFT
Education:Master's in Electrical/Electronics Engineering
Skills:DebugScriptingCollaboration
Tech Stack:DFTStructural DFTATPGMBISTDFT SynthesisDFT STA constraintsStatic timing analysisTiming closureScanShiftAtspeedSOC test STA methodologyAutomation scriptsSpyglassCDCLintRTL quality check tools

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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