Principal Product Engineer

Cadence Design Systems
Bengaluru, Noida
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 7-12 yearsEducation: bachelorsSkills: ["Debugging","Communication","Multitasking"]

Work as a Principal Product Engineer in the Digital and Signoff Group (DSG), collaborating with R&D and customer engagement teams to improve physical design performance on advanced chip designs. Apply deep knowledge of the physical design flow (netlist to GDSII) including floorplanning, power planning, placement, CTS, and routing, while diagnosing timing, congestion, power, and DRC issues. Manage benchmarks and communicate results and next steps for Innovus features.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Principal Product Engineer

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Last checked: 4 hours agoStatus: Live

Job Summary

Work as a Principal Product Engineer in the Digital and Signoff Group (DSG), collaborating with R&D and customer engagement teams to improve physical design performance on advanced chip designs. Apply deep knowledge of the physical design flow (netlist to GDSII) including floorplanning, power planning, placement, CTS, and routing, while diagnosing timing, congestion, power, and DRC issues. Manage benchmarks and communicate results and next steps for Innovus features.
Location: Bengaluru, Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Perform PPA improvement on critical customer designs.
  • •Apply end-to-end physical design expertise from netlist to GDSII, including floorplanng, power planning, placement, CTS, and routing.
  • •Diagnose timing, congestion, power optimization, routing, and DRC-related issues.
  • •Manage benchmarks and communicate issues, progress, and results to customers.
  • •Collaborate with R&D to discuss results and next steps for Innovus features.

Key Requirements

  • •BE/BTech/ME/MS/MTech or equivalent.
  • •7–12 years of experience in physical design and timing concepts.
  • •Strong knowledge of physical design flow from netlist to GDSII, including floorplanning, power planning, placement, CTS, and routing.
  • •Experience with advanced technology nodes (5nm and below; at least 7nm), with 3nm/2nm experience as a plus.
  • •Excellent debugging skills and ability to manage benchmarks while communicating issues and progress with customers.
Experience:7-12 years
Education:Bachelor's
Skills:DebuggingCommunicationMultitasking
Tech Stack:InnovusGDSIINetlistFloorplanningPower planningPlacementCTSRoutingTimingCongestionPower optimizationDRCs

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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