Lead Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Collaboration","Documentation"]

Implement and verify timing-closure for Palladium and Protium high-performance SoCs, driving work from RTL synthesis and floorplanning through clock tree construction and physical verification. Optimize timing, IR drop, and verification results to tape out. Collaborate with front-end RTL design teams and back-end verification teams, while reviewing and documenting designs for release.

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Cadence Design Systems
Cadence Design Systems
1 month ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Implement and verify timing-closure for Palladium and Protium high-performance SoCs, driving work from RTL synthesis and floorplanning through clock tree construction and physical verification. Optimize timing, IR drop, and verification results to tape out. Collaborate with front-end RTL design teams and back-end verification teams, while reviewing and documenting designs for release.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Implement and verify timing closure to tape out Palladium and Protium SoCs.
  • •Perform RTL synthesis and floorplanning activities.
  • •Build clock trees and run timing and IR drop optimizations.
  • •Conduct physical verification and close timing and IR drop.
  • •Review and document designs and interface with front-end RTL design and back-end verification teams.

Key Requirements

  • •BS in Electrical Engineering with at least 5 years of experience, or MS with at least 3 years of experience.
  • •Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus, and Pegasus.
  • •Experience with advanced process nodes like 5nm, 3nm, and 2nm.
  • •Experience using Linux servers and scripting with Shell/Perl/TCL/Python.
  • •Knowledge of industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, and UCIe.
Experience:5+ yearsElectronic designSoC verification
Education:Bachelor's in Electrical Engineering
Skills:CollaborationDocumentation
Tech Stack:Cadence InnovusCadence TempusQRCCadence VoltusPegasusRTL synthesisFloorplanningClock treesLinuxShellPerlTCLPythonLinux servers5nm3nm2nmPCI ExpressDDRLPDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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