RTL Design Engineer – Power Design

AMD
Austin
Workplace: HybridFull timeUSD 175,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Technical leadership","Ownership","Execution","Continuous improvement","Risk identification","Troubleshooting","Collaboration","Mentoring","Communication","Attention to detail","Cross-functional collaboration","Interpersonal skills"]

Join AMD’s Security IP (SECIP) design team to develop RTL-level IP power specifications and drive IP power targets through correlation of design intent with measurement results. Partner with SoC power leads, verification teams, and static power measurement groups to build simulation and regression infrastructure, improve power health metrics, and advance power architecture and methodology flows. Provide technical leadership while mentoring team members and best practices.

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FursaFursa
AMD
AMD
1 day ago

RTL Design Engineer – Power Design

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Join AMD’s Security IP (SECIP) design team to develop RTL-level IP power specifications and drive IP power targets through correlation of design intent with measurement results. Partner with SoC power leads, verification teams, and static power measurement groups to build simulation and regression infrastructure, improve power health metrics, and advance power architecture and methodology flows. Provide technical leadership while mentoring team members and best practices.
Location: Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop and maintain RTL-level IP power specifications and align IP power architecture with SoC power requirements with SoC, IP functional design, and power design teams.
  • •Define, track, and drive IP power targets by correlating power design intent with measurement results and identifying optimization opportunities.
  • •Collaborate with verification teams to develop power vectors for simulation-based power measurements.
  • •Partner with static power measurement teams to develop and maintain power regression infrastructure, monitor power health metrics, debug power-related issues, and analyze results to drive design improvements.
  • •Provide technical leadership in power architecture, design, analysis, and measurement methodology development, mentoring team members and promoting best practices across projects.

Pay and Benefits

Salary: USD 175,000 - 300,000 annually

Key Requirements

  • •Proficiency in Verilog/SystemVerilog and scripting languages such as Python, Tcl, Perl, and Ruby, along with Makefile-based development environments.
  • •Deep knowledge of modern RTL-level power architecture, design, analysis, measurement methodologies, and industry best practices.
  • •Strong understanding of microprocessor (MP) subsystem architectures, RTL microarchitectures for datapath accelerators, and low-power design methodologies.
  • •Solid understanding of industry-standard on-chip bus and interface protocols, including AMBA, AXI, and AHB.
  • •Experience with ASIC design and verification tools, including RTL simulation, linting, synthesis, power-aware verification, debugging, and related design flows.
Education:
Skills:Technical leadershipOwnershipExecutionContinuous improvementRisk identificationTroubleshootingCollaborationMentoringCommunicationAttention to detailCross-functional collaborationInterpersonal skills
Languages:En-us
Tech Stack:RTLPower designVerilogSystemVerilogPythonTclPerlRubyMakefileRTL simulationLintingSynthesisPower-aware verificationDebuggingASICAMBAAXIAHBStatic power measurementSimulation-based power measurements

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn