Senior DFT Logic Design Engineer

Intel
Phoenix, Santa Clara
Workplace: HybridFull timeUSD 141,910 - 269,100 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Customer-oriented","Self-driven","Analytical problem-solving","Communication","Teamwork"]

Provide technical support to Intel Foundry Services customers on PDKs and DFT/DFM insertion, including ATPG validation methodology and tool/flow guidance. Partner with internal teams, customers, IP providers, and EDA vendors to resolve issues and improve ASIC DFT/DFM quality. Create application notes and training, and drive block-level and SoC-level validation flow, capability, and documentation for successful customer tape-outs.

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Intel
Intel
3 days ago

Senior DFT Logic Design Engineer

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Last checked: 7 hours agoStatus: Live

Job Summary

Provide technical support to Intel Foundry Services customers on PDKs and DFT/DFM insertion, including ATPG validation methodology and tool/flow guidance. Partner with internal teams, customers, IP providers, and EDA vendors to resolve issues and improve ASIC DFT/DFM quality. Create application notes and training, and drive block-level and SoC-level validation flow, capability, and documentation for successful customer tape-outs.
Location: Phoenix, Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with internal teams and external stakeholders (foundry customers’ design teams, IP providers, EDA vendors) to resolve technical issues.
  • •Create content such as application notes and deliver technical training/presentations.
  • •Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for block and SoC levels.
  • •Support customers with tool/flow/methodology for successful tape-outs and to improve customer satisfaction.
  • •Provide tool/flow/methodology guidance and technical direction to streamline customer design work.

Pay and Benefits

Salary: USD 141,910 - 269,100 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •US Citizenship required and ability to obtain a US Government Security Clearance.
  • •Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or a STEM field.
  • •3+ years of experience implementing ASIC DFT/DFM insertion (e.g., MBIST, LBIST, SCAN, JTAG) at block and full-chip level, including ATPG validation and DFT timing/signoff at SoC level.
  • •4+ years of experience with scripting languages such as Python, Perl, Tcl, and/or shell scripting.
  • •Experience using major EDA tool suites for MBIST insertion, hierarchical SCAN/JTAG insertion, DFT constraint generation, and ATPG validation for single-die and multi-die designs (preferred).
Experience:Semiconductor foundryASIC designDFT/DFMAerospace defense government
Education:Bachelor's in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
Skills:Customer-orientedSelf-drivenAnalytical problem-solvingCommunicationTeamwork
Tech Stack:Intel FoundryPDKsDFT/DFM insertionATPG validationMBISTLBISTSCANJTAGASIC designSoC levelCMOS processesPythonPerlTclShell scriptingEDA tool suitesHierarchical SCANDFT constraint generationDFT timing signoffTape-outs

Eligibility

Security Clearance:US Government Security ClearanceSecret

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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