Mixed-Signal IC Design Engineer

Arago
Paris, Tel Aviv
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Teamwork","Problem-solving"]

Design, integrate, and deliver high-performance digital subsystems for mixed-signal ICs, driving RTL-to-tape-out flow and collaborating with analog/layout teams to optimize digital-analog boundaries. Owns calibration, high-speed data paths, and SerDes-related work, interfacing with external IP blocks while leveraging strong RTL design and EDA toolchains. English proficiency required; French a plus.

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FursaFursa
Arago
Arago
1 year ago

Mixed-Signal IC Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Design, integrate, and deliver high-performance digital subsystems for mixed-signal ICs, driving RTL-to-tape-out flow and collaborating with analog/layout teams to optimize digital-analog boundaries. Owns calibration, high-speed data paths, and SerDes-related work, interfacing with external IP blocks while leveraging strong RTL design and EDA toolchains. English proficiency required; French a plus.
Location: Paris, Tel Aviv
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines, control FSMs, data converters, and multiplexing logic.
  • •Integrate and customize external IP blocks (e.g., GPIOs, LVDS I/Os, serial interfaces), ensuring compliance with analog signal and timing requirements.
  • •Lead the digital implementation flow for mixed-signal blocks: from RTL to synthesis, floorplanning, P&R, timing closure, physical signoff, and tape-out.
  • •Collaborate closely with analog, layout, and system teams to co-optimize digital-analog boundaries, resolve cross-domain issues, and ensure robust high-speed performance.
  • •Contribute to the development of high-speed serial I/O subsystems — experience in the design and implementation of SerDes blocks is a significant advantage.

Pay and Benefits

Equity and Bonus:Equity
Perks:Health InsurancePensionEquityRelocationPaid Leave

Key Requirements

  • •Strong experience in digital RTL design (Verilog/SystemVerilog) for mixed-signal systems with high-speed calibration/control loops, converters, multiplexers, and serial/parallel data paths.
  • •Deep understanding of digital-analog integration challenges, including timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning in high-speed environments.
  • •Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, and tape-out, especially in analog or RF IC contexts.
  • •Skilled in integrating external IPs such as GPIOs, LVDS, SPI/I2C interfaces; SerDes experience is highly valued.
  • •Proficient with industry-standard EDA toolchains for front-end and back-end, with strong mixed-signal layout constraints knowledge.
Experience:SemiconductorsElectronics
Skills:CommunicationTeamworkProblem-solving
Languages:EnglishFrench
Tech Stack:VerilogSystemVerilogRTLSerDesLVDSSPII2CEDAFloorplanningP&RTiming closure

Company Brief

Arago
Develops energy-efficient photonic AI processors (codenamed “JEF”) that use light-based computation to drastically reduce energy consumption for AI workloads, targeting data centers and large-scale inference deployments.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Early Stage Startup
Funding: Seed
Headquarters: Paris, France
Founded: 2024
Glassdoor
Glassdoor: 3.9
WebsiteGlassdoor