STAFF ENG-HBM-LAYOUT

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8-15 yearsEducation: bachelorsSkills: ["Leadership","Planning","Scheduling","Delegation","Communication","Problem-solving","Detail orientation"]

Design and develop mixed-signal and custom digital block layouts for full-chip integration in Micron’s HBM team, collaborating with global engineering and packaging/scribe design partners. Own critical objectives including PWF reticle design and TSV engagement, create and maintain DFMEA for advanced packaging steps, and perform physical verification (LVS/DRC/Antenna) with quality documentation. Lead planning and execution across multiple layout projects, guiding junior engineers to meet tapeout milestones.

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FursaFursa
Micron Technology
Micron Technology
1 week ago

STAFF ENG-HBM-LAYOUT

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Design and develop mixed-signal and custom digital block layouts for full-chip integration in Micron’s HBM team, collaborating with global engineering and packaging/scribe design partners. Own critical objectives including PWF reticle design and TSV engagement, create and maintain DFMEA for advanced packaging steps, and perform physical verification (LVS/DRC/Antenna) with quality documentation. Lead planning and execution across multiple layout projects, guiding junior engineers to meet tapeout milestones.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Design and develop critical design and co-optimization objectives for mixed-signal/custom digital blocks and full-chip integration support.
  • •Build and tapeout PWF reticles design.
  • •Engage with scribe design teams to capture advanced packaging requirements and review results.
  • •Coordinate TSV design engagement with HIG-HBM DTPCO teams covering electrical, thermal, and mechanical performance.
  • •Perform layout verification (LVS/DRC/Antenna), quality checks/documentation, and deliver on-time block-level layouts while planning and guiding junior engineers.

Pay and Benefits

Perks:Paid LeaveLearning BudgetWellness StipendHealth Insurance

Key Requirements

  • •8 to 15 years of analog/custom IC layout experience in advanced CMOS (Planar, FinFET) across technology nodes.
  • •Expertise in Cadence VLE/VXL and Mentor Graphic Calibre for DRC/LVS.
  • •Hands-on layout creation for critical blocks such as PLL, ADC, DAC, LDO, bandgap, reference generators, and comparators.
  • •Experience with reticle development and full chip verification/tapeout support.
  • •Ability to automate or use AI features for efficient project execution and strong layout fundamentals for parasitics and effects (e.g., IR-drop, crosstalk).
Experience:8-15 yearsSemiconductorsIC layoutAnalog/custom layoutHBMAdvanced CMOSTapeout
Education:Bachelor's in Electronic/VLSI Engineering
Skills:LeadershipPlanningSchedulingDelegationCommunicationProblem-solvingDetail orientation
Tech Stack:Cadence VLECadence VXLMentor Graphic CalibreDRCLVSAntennaDFMEAPWFTSVPWF ReticlesScribe DesignPlanarFinFET

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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