Principal DFT Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeUSD 146,000 - 309,000 annuallyFunction: Communications, PR & CommunityExperience: 7+ yearsEducation: bachelorsSkills: ["Collaboration","Debugging","Process improvement","Attention to detail"]

Own DFT architecture, implementation, and signoff for complex HBM base-die SoCs. Drive scan/MBIST/LBIST and boundary-scan (JTAG) test access planning early, then implement DFT logic across block to full-chip levels. Execute DFT flow checks (lint, CDC, DFT rules, ATPG readiness, coverage closure), partner with physical design, and support pre-/post-silicon debug and yield analysis. Collaborate with CAD to standardize DFT flows across HBM SoC programs.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
1 week ago

Principal DFT Engineer, HBM

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Own DFT architecture, implementation, and signoff for complex HBM base-die SoCs. Drive scan/MBIST/LBIST and boundary-scan (JTAG) test access planning early, then implement DFT logic across block to full-chip levels. Execute DFT flow checks (lint, CDC, DFT rules, ATPG readiness, coverage closure), partner with physical design, and support pre-/post-silicon debug and yield analysis. Collaborate with CAD to standardize DFT flows across HBM SoC programs.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Own SoC-level DFT implementation including scan, MBIST/LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs.
  • •Define DFT architecture early in the design cycle and ensure alignment with integration, floorplanning, timing, power, and physical design constraints.
  • •Implement and integrate DFT logic at block, subsystem, and full-chip levels working with RTL and integration teams.
  • •Execute DFT flow and signoff including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
  • •Collaborate with physical design, verification, product engineering, test/probe, and manufacturing teams to ensure testability and support pre-/post-silicon bring-up, debug, and yield analysis.

Pay and Benefits

Salary: USD 146,000 - 309,000 annually
Perks:Health InsuranceDentalVisionPaid Time-offPaid HolidaysParental Leave

Key Requirements

  • •Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
  • •7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs/SoCs.
  • •Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
  • •Familiarity with full RTL-to-GDS SoC flows and interactions between DFT, synthesis, STA, and physical design.
  • •Proficiency with industry-standard EDA tools (Siemens, Synopsys, and/or Cadence) and scripting (Python, Tcl, Perl) for flow automation.
Experience:7+ years
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:CollaborationDebuggingProcess improvementAttention to detail
Tech Stack:HBMDFTSoCScan insertionMBISTLBISTJTAGBoundary scanATPGRTL-to-GDSSTASiemens EDASynopsysCadencePythonTclPerlLintCDCATPG readiness

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn