Manager, Advanced Packaging Design Enablement Engineering (APDEE)

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: phdSkills: ["Leadership","Mentorship","Cross-functional collaboration","Technical communication","Problem-solving"]

Lead die design and layout engineering for Micron’s High Bandwidth Memory (HBM) advanced packaging programs. Own die-level design strategy from concept through tape-out and post-silicon validation, define die floorplanning and design rules, and manage sign-off flows. Guide a team of die build and layout engineers while bridging silicon design, packaging/process integration, and product engineering to drive performance, yield, reliability, and time-to-market.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
3 months ago

Manager, Advanced Packaging Design Enablement Engineering (APDEE)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Lead die design and layout engineering for Micron’s High Bandwidth Memory (HBM) advanced packaging programs. Own die-level design strategy from concept through tape-out and post-silicon validation, define die floorplanning and design rules, and manage sign-off flows. Guide a team of die build and layout engineers while bridging silicon design, packaging/process integration, and product engineering to drive performance, yield, reliability, and time-to-market.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead, mentor, and grow a team of die build and layout engineers with clear goals and performance expectations.
  • •Own end-to-end die design and layout strategy for HBM die programs from concept through tape-out and post-silicon validation.
  • •Define die floorplanning strategy including TSV grid placement, micro-bump array layout, power domain partitioning, and KOZ management.
  • •Establish and maintain die design rules aligned to foundry PDK requirements and advanced packaging process constraints.
  • •Drive technical contributions across PWF reticles/tapeout, DFT development for packaging fail modes, electrical simulations, and DFMEA creation/maintenance for packaging process steps.

Key Requirements

  • •Masters or PhD in Electrical Engineering, Computer Engineering, or a related field required.
  • •10+ years of experience in die design and physical layout engineering.
  • •5+ years in a lead or management role overseeing layout engineering teams.
  • •Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent).
  • •Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL.
Experience:10+ yearsHBM3D-ICAdvanced packagingMemory interfaces
Education:PhD / Doctorate in Electrical Engineering, Computer Engineering
Skills:LeadershipMentorshipCross-functional collaborationTechnical communicationProblem-solving
Tech Stack:Cadence VirtuosoInnovusMentor CalibreSynopsys IC CompilerSkillPythonTclDFMEA

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn