ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)

Cisco
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12-16 yearsEducation: mastersSkills: ["Technical leadership","Teamwork","Communication","Organizational skills","Analytical/problem-solving"]

Lead digital design for Cisco’s Client Optics Group, shaping ASIC/SoC digital logic for silicon photonics and high-speed optical interconnects. Manage the full ASIC lifecycle from RTL-based CPU subsystem and data-path interface architecture through tapeout and post-silicon bring-up, including FPGA prototyping and lab validation. Drive integration of digital logic with analog/mixed-signal blocks, oversee verification coverage and signoff, and collaborate across firmware, packaging, and process teams to optimize performance, power, and manufacturability.

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FursaFursa
Cisco
Cisco
3 months ago

ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)

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Job Summary

Lead digital design for Cisco’s Client Optics Group, shaping ASIC/SoC digital logic for silicon photonics and high-speed optical interconnects. Manage the full ASIC lifecycle from RTL-based CPU subsystem and data-path interface architecture through tapeout and post-silicon bring-up, including FPGA prototyping and lab validation. Drive integration of digital logic with analog/mixed-signal blocks, oversee verification coverage and signoff, and collaborate across firmware, packaging, and process teams to optimize performance, power, and manufacturability.
Location: Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead all design activities from pre-silicon RTL to GDS2 signoff and post-silicon activities such as FPGA prototyping, lab validation, and ATE bring-up.
  • •Architect and design complex digital blocks and CPU subsystems, collaborating across cross-functional teams and resolving technical issues.
  • •Oversee integration of digital logic with analog and mixed-signal blocks to support reliability of co-packaged optics and silicon photonics modules.
  • •Drive verification strategy: review coverage, sign off on coverage metrics, independently simulate/verify/debug issues, and support integration and verification of SerDes and DSP IP.
  • •Support backend activities including synthesis, timing closure, DFT, low-power design, and design automation scripts to improve QOR metrics; contribute to FPGA prototyping and validation as applicable.

Key Requirements

  • •Bachelor’s or master’s degree in electrical engineering, electronics engineering, or a related field (master’s strongly preferred).
  • •12–16 years of industry experience with hands-on digital design, including FSM and CPU sub-systems for complex SOCs and FPGA validation.
  • •Strong technical leadership experience (minimum 6 years).
  • •Strong knowledge of the ASIC/SoC design flow, including RTL development using SystemVerilog, simulation/lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff.
  • •Familiarity with protocols such as SPI, I2C, APB, AXI (or similar) and high-speed SerDes, Ethernet, and D2D PHY IP/protocols.
Experience:12-16 yearsSemiconductorsASIC/SoCSilicon photonicsFPGA validation
Education:Master's in Electrical engineering / Electronics Engineering (or related)
Skills:Technical leadershipTeamworkCommunicationOrganizational skillsAnalytical/problem-solving
Tech Stack:SystemVerilogRTLFSMASIC/SoCSimulationLintCDC/RDCSynthesisFormal/equivalence checkingDFTImplementation handoffLECGDS2FPGA prototypingLab validationATE bring-upSPII2CAPBAXI

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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