ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12-16 yearsEducation: mastersSkills: ["Technical leadership","Teamwork","Communication","Organizational skills","Analytical/problem-solving"]Lead digital design for Cisco’s Client Optics Group, shaping ASIC/SoC digital logic for silicon photonics and high-speed optical interconnects. Manage the full ASIC lifecycle from RTL-based CPU subsystem and data-path interface architecture through tapeout and post-silicon bring-up, including FPGA prototyping and lab validation. Drive integration of digital logic with analog/mixed-signal blocks, oversee verification coverage and signoff, and collaborate across firmware, packaging, and process teams to optimize performance, power, and manufacturability.
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