Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["Leadership","Communication","Problem-solving"]

Lead design verification efforts for complex hardware designs, developing and maintaining UVM/SystemVerilog verification environments, crafting test plans, and driving verification closure from concept to delivery in a CADENCE hardware/EDA setting. Collaborate with cross-functional teams to validate memory IP and ensure robust functional verification of complex designs.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Lead Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Lead design verification efforts for complex hardware designs, developing and maintaining UVM/SystemVerilog verification environments, crafting test plans, and driving verification closure from concept to delivery in a CADENCE hardware/EDA setting. Collaborate with cross-functional teams to validate memory IP and ensure robust functional verification of complex designs.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead design verification activities for complex designs from concept through verification closure.
  • •Develop and maintain verification environments using UVM and SystemVerilog.
  • •Create and execute test plans and environment development to validate functionality.
  • •Collaborate with design teams across the lifecycle to debug and drive verification closure.
  • • Manage projects and coordinate with cross-functional teams to ensure on-time delivery.

Key Requirements

  • •BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • •4+ years of Design Verification experience with SV/UVM
  • •Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • •Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • •Strong hands-on UVM and SystemVerilog coding experience and functional verification environment development is required.
Experience:4+ yearsSemiconductorHardware designEDA
Education:Bachelor's in Electrical / Electronics / VLSI
Skills:LeadershipCommunicationProblem-solving
Tech Stack:SystemVerilogUVMSVVerification

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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