Principal Design Engineer

Cadence Design Systems
Hyderabad, Noida, Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10-17 yearsEducation: bachelorsSkills: ["Communication","Leadership","Problem-solving","Technical execution","Mentoring"]

Architect and design high-speed Analog/Mixed-Signal IP and subsystems for next-generation connectivity and memory interfaces. Lead design closure across TX/RX, PLL/DLL/CDR, clocking, datapath, I/O, and interfaces, while coordinating cross-functional teams across Analog Design, Layout, verification, Digital, and Physical Design. Mentor engineers, drive technical excellence, and take ownership of complex IP programs from architecture through silicon delivery.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Principal Design Engineer

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Job Summary

Architect and design high-speed Analog/Mixed-Signal IP and subsystems for next-generation connectivity and memory interfaces. Lead design closure across TX/RX, PLL/DLL/CDR, clocking, datapath, I/O, and interfaces, while coordinating cross-functional teams across Analog Design, Layout, verification, Digital, and Physical Design. Mentor engineers, drive technical excellence, and take ownership of complex IP programs from architecture through silicon delivery.
Location: Hyderabad, Noida, Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems.
  • •Drive design closure for TX/RX, PLL, DLL, CDR, clocking, datapath, I/O, and interface circuits.
  • •Lead complex IP programs with cross-functional teams including Analog Design, Layout, AMS Verification, Digital, and Physical Design.
  • •Mentor engineers and drive technical excellence, innovation, and execution.
  • •(If applicable) Lead project execution, staffing, risk management, and customer engagements for management roles.

Key Requirements

  • •10–17+ years of experience in analog/mixed-signal or high-speed interface design and delivery.
  • •Strong expertise in high-speed interface design for UCIe / Die-to-Die (D2D).
  • •Experience with PCIe Gen3/4/5/6 and SerDes architectures.
  • •Knowledge of DDRx/LPDDRx/GDDRx/HBM (and related memory interface technologies).
  • •Ability to drive SI/PI, ESD, Reliability, Jitter, Timing, and PPA optimization and deliver complex IPs from architecture to silicon.
Experience:10-17 yearsHigh-speed interfacesAnalog/Mixed-SignalIP developmentAIHPCNetworkingData Center
Education:Bachelor's
Skills:CommunicationLeadershipProblem-solvingTechnical executionMentoring
Tech Stack:UCIeDie-to-Die (D2D)PCIeDDRxLPDDRxGDDRxHBMGDDRSerDesPLLDLLCDRClockingDatapathI/OSI/PIESDReliabilityJitterTiming

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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