Senior/Staff ASIC Engineer

Micron Technology
Taiwan
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsSkills: ["Problem-solving","Cross-team collaboration","Communication","Automation mindset","Curiosity","Debugging"]

Own full-chip SoC integration from RTL to silicon, spanning front-end and back-end flows. Drive adoption of AI/ML techniques to automate integration tasks such as RTL analysis, constraint generation, and design rule checking, while improving design quality and reducing issue turnaround. Execute SoC integration disciplines (lint/CDC/DFT/STA/GLS/power/UPF/formal verification/ECO), collaborate across design teams, and develop automation scripts to accelerate repeatable workflows.

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FursaFursa
Micron Technology
Micron Technology
1 month ago

Senior/Staff ASIC Engineer

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Last checked: 7 hours agoStatus: Live

Job Summary

Own full-chip SoC integration from RTL to silicon, spanning front-end and back-end flows. Drive adoption of AI/ML techniques to automate integration tasks such as RTL analysis, constraint generation, and design rule checking, while improving design quality and reducing issue turnaround. Execute SoC integration disciplines (lint/CDC/DFT/STA/GLS/power/UPF/formal verification/ECO), collaborate across design teams, and develop automation scripts to accelerate repeatable workflows.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Perform full-chip SoC integration across front-end and back-end design flows, taking designs from RTL toward silicon readiness.
  • •Drive adoption of AI/ML to automate and optimize integration workflows, including AI-assisted RTL analysis, constraint generation, design rule checking, scripting, debugging, and root-cause analysis.
  • •Contribute to one or more integration disciplines such as lint/RTL quality checks, CDC analysis, DFT (scan insertion/ATPG/MBIST), timing constraints & STA, gate-level simulation, power estimation/analysis, UPF/multi-voltage verification, and formal verification/ECO.
  • •Collaborate with RTL, physical design, DFT, analog/IP, and verification teams to resolve integration issues and improve signoff readiness.
  • •Develop and improve automation scripts (Tcl/Python/Perl) and evaluate AI/ML/agentic workflows for EDA applications; support silicon bring-up debug when needed.

Key Requirements

  • •Bachelor’s (8+ years) or Master’s (6+ years) or PhD (2+ years) in Electrical Engineering, Computer Engineering, or Computer Science.
  • •Hands-on experience in at least one SoC integration area such as lint/CDC/DFT/timing constraints/STA/gate-level simulation/power estimation/UPF/formal verification/ECO.
  • •Strong interest in applying AI and automation to chip design workflows, including willingness to experiment with LLMs and ML models.
  • •Familiarity with industry-standard EDA tools including Spyglass, Conformal, Tessent, PrimeTime/Tempus, VCS/Xcelium, and Joules/PowerArtist.
  • •Proficiency in scripting (Tcl, Python, or Perl) and ability to collaborate and communicate across engineering teams.
Experience:8+ yearsSoCRTLASICEDAAI/MLChip designSoC integrationFormal verification
Education:
Skills:Problem-solvingCross-team collaborationCommunicationAutomation mindsetCuriosityDebugging
Languages:EnglishMandarin
Tech Stack:SoC integrationRTLSilicon validationAIMachine learningLarge language modelsLLMSpyiagassAscentSpyglassConformalTessentPrimeTimeTempusVCSXceliumJoulesPowerArtistTclPython

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
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