Senior SoC Digital Verification Engineer, Multimedia Lab

Build and scale verification for FPGA/ASIC video codec hardware solutions, from module-level through SoC system-level test planning and execution. Create reusable UVM-based verification environments and components, run constrained-random and directed tests, and drive functional and code coverage to closure. Own GLS and SDF back-annotated timing simulation, support emulation/FPGA co-debugging, and optimize regression automation to improve verification efficiency and compute utilization.