Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab

ByteDance
San Jose
Workplace: OnsiteFull timeFunction: Creative Production (Video/Audio/Photo)Experience: 5+ yearsEducation: mastersSkills: []

Design and implement high-performance, low-power video codec hardware IPs within the Video Silicon IP team. Collaborate with algorithm, architecture, software, firmware, and verification experts to translate codec standards into implementable hardware micro-architectures. Own RTL development for codec pipeline stages, drive UVM-based functional correctness and coverage closure, and support synthesis, timing analysis, and CDC/RDC checks to meet stringent area, power, and performance (PPA) targets.

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FursaFursa
ByteDance
ByteDance
1 month ago

Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 30 days agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Design and implement high-performance, low-power video codec hardware IPs within the Video Silicon IP team. Collaborate with algorithm, architecture, software, firmware, and verification experts to translate codec standards into implementable hardware micro-architectures. Own RTL development for codec pipeline stages, drive UVM-based functional correctness and coverage closure, and support synthesis, timing analysis, and CDC/RDC checks to meet stringent area, power, and performance (PPA) targets.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Creative Production (Video/Audio/Photo)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with architecture, algorithm, and verification teams to build high performance, low power video processing IPs.
  • •Create ASIC designs for compressing and processing still images and videos using computer architecture and ASIC design knowledge.
  • •Develop micro-architectures to meet area, power, and performance (PPA) targets for multi-standard codec cores.
  • •Design and implement RTL for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding, and in-loop filters.
  • •Partner with verification on directed and constrained-random UVM testing to ensure functional correctness, then debug and close RTL coverage metrics.

Key Requirements

  • •M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • •5 years of ASIC front-end design experience as a primary RTL owner.
  • •Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
  • •Familiarity with UVM/DPI/C++.
  • •Solid understanding of VLSI design concepts including pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
Experience:5+ yearsVideo codecASIC designVLSIFPGA prototyping
Education:Master's in Electrical Engineering or Computer Engineering
Tech Stack:FPGAASICVideo codecRTLSystemVerilogVerilogUVMDPIC++VLSIPipeliningClock gatingMemory architectureAXIAPBSV assertionsPythonEDAHLSUVM test benches

Company Brief

ByteDance
Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Established Company
Headquarters: Beijing, China
Founded: 2012
WebsiteLinkedIn