NVIDIA

3 weeks ago

Senior Physical Design and Timing Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 20 hours agoStatus: Live

Job Summary

Drive physical design and timing for high-frequency, low-power NVIDIA CPUs, GPUs, LPUs, and SoCs from RTL through GDS2. Own synthesis, equivalence checking, floor-planning, timing constraints, timing/power convergence, and ECO implementation, working closely with multiple teams. Improve convergence flows with the Methodology Team and apply expertise in STA, critical path planning, DFT closure, and deep-submicron signal integrity and variation-aware optimization using industry-standard EDA tools and scripting.

Location: Santa Clara, Austin, Durham

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Drive physical design and timing across block, cluster, and full-chip levels for NVIDIA CPUs/GPUs/LPUs/SoCs.
•Lead frontend and backend implementation from RTL to GDS2, covering synthesis, equivalence checking, floor-planning, timing constraints, timing/power convergence, and ECOs.
•Collaborate in a cross-functional environment interacting with multiple teams.
•Apply knowledge to improve convergence flows with the Methodology Team.
•Use expertise in timing/power optimization and signal integrity/variation-aware analysis to achieve timing closure.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Key Requirements

•BS (or equivalent) in Electrical or Computer Engineering with 5+ years experience, or MS (or equivalent) with 3+ years experience in synthesis and timing.
•Solid experience with full-chip/sub-chip Static Timing Analysis (STA), including timing constraints generation/management and timing convergence.
•Hands-on experience in logic synthesis and equivalence checking/formal verification, with RTL/logic design skills for timing closure.
•Expertise in physical design optimization (placement, routing, cell sizing, buffering, logic restructuring) and implementing improvements through ECOs.
•Knowledge in DFT logic and design closure, including DFT timing closure experience (scan shift/capture, transition faults, BIST) plus analysis of crosstalk/noise/glitch and process variation effects.

Experience:3+ yearsSemiconductorHardware design

Education:Bachelor's

Skills:Cross-functional collaborationAutonomyContinuous improvement

Tech Stack:RTLGDS2SynthesisEquivalence checkingFloor-planningTiming constraintsECOStatic Timing AnalysisSTADFTPerlTclMakePythonEDA tools

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

3 weeks ago

Senior Physical Design and Timing Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 20 hours agoStatus: Live

Job Summary

Location: Santa Clara, Austin, Durham

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Drive physical design and timing across block, cluster, and full-chip levels for NVIDIA CPUs/GPUs/LPUs/SoCs.
•Lead frontend and backend implementation from RTL to GDS2, covering synthesis, equivalence checking, floor-planning, timing constraints, timing/power convergence, and ECOs.
•Collaborate in a cross-functional environment interacting with multiple teams.
•Apply knowledge to improve convergence flows with the Methodology Team.
•Use expertise in timing/power optimization and signal integrity/variation-aware analysis to achieve timing closure.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Key Requirements

•BS (or equivalent) in Electrical or Computer Engineering with 5+ years experience, or MS (or equivalent) with 3+ years experience in synthesis and timing.
•Solid experience with full-chip/sub-chip Static Timing Analysis (STA), including timing constraints generation/management and timing convergence.
•Hands-on experience in logic synthesis and equivalence checking/formal verification, with RTL/logic design skills for timing closure.
•Expertise in physical design optimization (placement, routing, cell sizing, buffering, logic restructuring) and implementing improvements through ECOs.
•Knowledge in DFT logic and design closure, including DFT timing closure experience (scan shift/capture, transition faults, BIST) plus analysis of crosstalk/noise/glitch and process variation effects.

Experience:3+ yearsSemiconductorHardware design

Education:Bachelor's

Skills:Cross-functional collaborationAutonomyContinuous improvement

Tech Stack:RTLGDS2SynthesisEquivalence checkingFloor-planningTiming constraintsECOStatic Timing AnalysisSTADFTPerlTclMakePythonEDA tools

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor