Design Verification Engineer - Internal IP

Etched
San Jose
Workplace: OnsiteFull timeUSD 150,000 - 275,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Problem-solving","Collaboration","Communication","Attention to detail","Debugging"]

Design Verification Engineer to join Etched’ s Internal IP DV team, focusing on robust, high-performance verification of custom IPs (systolic arrays, DMAs, NoCs). You’ll develop UVM testbenches, define verification plans, debug complex datapath issues, and collaborate across RTL, architecture, and SW teams to ensure silicon-ready functionality from end-to-end. This role blends hardware design verification with cross-team coordination in a fast-paced ASIC environment.

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FursaFursa
Etched
Etched
1 year ago

Design Verification Engineer - Internal IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Design Verification Engineer to join Etched’ s Internal IP DV team, focusing on robust, high-performance verification of custom IPs (systolic arrays, DMAs, NoCs). You’ll develop UVM testbenches, define verification plans, debug complex datapath issues, and collaborate across RTL, architecture, and SW teams to ensure silicon-ready functionality from end-to-end. This role blends hardware design verification with cross-team coordination in a fast-paced ASIC environment.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
  • •Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
  • •Debug complex datapath and protocol issues in RTL and testbench environments.
  • •Work closely with architects and designers to validate functionality and design intent.
  • •Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually
Equity and Bonus:Equity
Perks:MedicalDentalVisionHousing SubsidyRelocationWellness Stipend

Key Requirements

  • •Proficiency with UVM and SystemVerilog.
  • •Strong debugging and problem-solving skills for complex digital designs.
  • •Solid knowledge of computer architecture and digital design fundamentals.
  • •Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
  • •Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques (Nice-to-have)
Experience:HardwareASICAI hardware
Skills:Problem-solvingCollaborationCommunicationAttention to detailDebugging
Tech Stack:UVMSystemVerilogSystemVerilog Assertions (SVA)PythonPerlTCLNoCAXIDMASystolic arraysMemory subsystems

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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