1 week ago

Senior Speed Characterization Engineer - Silicon Co-Design Group

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin/Vmax, and timing margins across the full PVT space. Close the prediction-to-silicon correlation gap by tying pre-silicon timing analysis to measured silicon and quantifying divergences. Trace frequency misses and failures to their sources, and build AI agent–driven test orchestration, data pipelines, and analysis flows that expand coverage and reduce cycle time.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own silicon speed characterization from first power-on through production sign-off across the full PVT space, including frequency, Vmin/Vmax, and timing margins.
•Close the correlation gap by tying pre-silicon timing analysis and critical path predictions to measured silicon and producing actionable analysis for architecture and design.
•Trace failures to their source—such as microarchitectural bottlenecks, non-closing critical paths under voltage, clocking issues, or unanticipated process corners—and drive resolution.
•Own and build AI agent-driven workflows for automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time.
•Provide data-driven tradeoff analysis across architecture, VLSI, ASIC, firmware, and product teams to settle key decisions.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually

Equity and Bonus:Equity

Key Requirements

•BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
•5+ years hands-on silicon experience including bring-up, post-silicon speed validation, frequency characterization, or timing analysis on real hardware.
•Strong computer architecture fundamentals, including pipeline structures, clocking, and memory hierarchies, and how microarchitectural decisions affect frequency and power.
•Depth in static timing analysis and critical path identification, with the ability to read and reason about timing reports at the block and chip level.
•Proficiency in silicon margining, guard-banding, and PVT/binning dependencies, plus scripting depth in Python, Perl, or C/C++.

Experience:5+ years

Education:Bachelor's in Electrical Engineering, Computer Engineering, or Systems Engineering

Skills:Static timing analysisData analysisStatistical fluency

Tech Stack:PythonPerlC/C++Static timing analysisVLSIASICFirmware

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

1 week ago

Senior Speed Characterization Engineer - Silicon Co-Design Group

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own silicon speed characterization from first power-on through production sign-off across the full PVT space, including frequency, Vmin/Vmax, and timing margins.
•Close the correlation gap by tying pre-silicon timing analysis and critical path predictions to measured silicon and producing actionable analysis for architecture and design.
•Trace failures to their source—such as microarchitectural bottlenecks, non-closing critical paths under voltage, clocking issues, or unanticipated process corners—and drive resolution.
•Own and build AI agent-driven workflows for automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time.
•Provide data-driven tradeoff analysis across architecture, VLSI, ASIC, firmware, and product teams to settle key decisions.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually

Equity and Bonus:Equity

Key Requirements

•BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
•5+ years hands-on silicon experience including bring-up, post-silicon speed validation, frequency characterization, or timing analysis on real hardware.
•Strong computer architecture fundamentals, including pipeline structures, clocking, and memory hierarchies, and how microarchitectural decisions affect frequency and power.
•Depth in static timing analysis and critical path identification, with the ability to read and reason about timing reports at the block and chip level.
•Proficiency in silicon margining, guard-banding, and PVT/binning dependencies, plus scripting depth in Python, Perl, or C/C++.

Experience:5+ years

Education:Bachelor's in Electrical Engineering, Computer Engineering, or Systems Engineering

Skills:Static timing analysisData analysisStatistical fluency

Tech Stack:PythonPerlC/C++Static timing analysisVLSIASICFirmware

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor