DFT Application Engineer

Intel
United States
Workplace: HybridFull timeUSD 122,440 - 232,190 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Customer-focused","Self-motivated","Collaborative","Analytical problem-solving","Communication"]

Support Intel Foundry Services customers with DFT/DFM and ATPG validation methodologies for successful ASIC tape-outs. Provide DFT tool/flow guidance, collaborate with internal and external teams (design, IP, EDA vendors) to resolve technical issues, and lead quality improvements from block-level to SoC-level. Develop DFT insertion flows for advanced CMOS and multi-die designs, and create application notes and customer-facing technical training.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Intel
Intel
7 months ago

DFT Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Support Intel Foundry Services customers with DFT/DFM and ATPG validation methodologies for successful ASIC tape-outs. Provide DFT tool/flow guidance, collaborate with internal and external teams (design, IP, EDA vendors) to resolve technical issues, and lead quality improvements from block-level to SoC-level. Develop DFT insertion flows for advanced CMOS and multi-die designs, and create application notes and customer-facing technical training.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Provide comprehensive DFT tool/flow/methodology support to resolve customer issues and enable successful tape-outs.
  • •Collaborate with internal Intel teams and external stakeholders (customer design teams, IP providers, EDA vendors) to resolve complex technical DFT problems.
  • •Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology and documentation for block-level and SoC-level implementations.
  • •Partner with RTL and Hard IP designers and physical designers on DFT/DFM implementation, validation, and timing signoff.
  • •Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs, and deliver application notes and technical training.

Pay and Benefits

Salary: USD 122,440 - 232,190 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •US Citizenship required.
  • •Ability to obtain US Government Security Clearance.
  • •Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field.
  • •3+ years of experience with advanced CMOS processes (22nm and below).
  • •3+ years implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) and ATPG validation/DFT timing/signoff at block and full-chip (SoC) levels; plus 2+ years scripting in Python, Perl, Tcl and/or shell.
Experience:SemiconductorsASICFoundry servicesAerospace defenseEDA
Education:Bachelor's in Electrical Engineering, Computer Engineering, or STEM-related field
Skills:Customer-focusedSelf-motivatedCollaborativeAnalytical problem-solvingCommunication
Tech Stack:DFTDFMATPGPDKsMBISTLBISTSCANJTAGRTLHard IPEDA toolsPythonPerlTclShell scriptingASICSoCCMOSLVSDRC

Eligibility

Security Clearance:Secret

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
WebsiteLinkedInGlassdoor