SDC, Synthesis and STA Engineer

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Debugging","Collaboration","Technical guidance","Planning","Quality delivery"]

Own front-end implementation for IPs, including SDC development, generation, verification, promotion/demotion, and equivalence checking. Lead SDC/constraint closure for IPs, SS, and SoCs, coordinating with design and PNR teams to meet schedule and quality targets. Support synthesis, LEC, CLP, and pre/post-layout STA or timing closure as needed, while debugging technical issues and ensuring timing, low-power, and DFT concepts are correctly applied.

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FursaFursa
AMD
AMD
18 hours ago

SDC, Synthesis and STA Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Own front-end implementation for IPs, including SDC development, generation, verification, promotion/demotion, and equivalence checking. Lead SDC/constraint closure for IPs, SS, and SoCs, coordinating with design and PNR teams to meet schedule and quality targets. Support synthesis, LEC, CLP, and pre/post-layout STA or timing closure as needed, while debugging technical issues and ensuring timing, low-power, and DFT concepts are correctly applied.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Own SDC development for IPs, including SDC generation, verification, promotion/demotion, and equivalence checking.
  • •Own constraints for IPs, SS, and SoCs and ensure complete quality delivery for synthesis and timing closure.
  • •Perform or support front-end implementation tasks such as synthesis, LEC, CLP, and prelayout STA/postlayout STA timing closure as needed.
  • •Coordinate with design and PNR teams to achieve closure and plan execution according to required duration and schedule.
  • •Debug and resolve technical issues related to constraints, timing, and related verification/synthesis flows.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Plan and execute front-end implementation for IPs, including SDC ownership through generation, verification, promotion/demotion, and equivalence checking.
  • •Experience with synthesis, LEC, CLP, and STA/timing closure (including prelayout and postlayout where needed).
  • •Prior experience with Lint, CDC, RTL and RTL/netlist-based static checks is preferred.
  • •Strong understanding of timing constraints plus low-power aspects and DFT concepts.
  • •Bachelors with 8 years of experience in Electrical Engineering or a Masters degree with 6 years of experience in Electrical Engineering.
Experience:8+ yearsEDAHardware design automation
Education:Bachelor's in Electrical Engineering
Skills:DebuggingCollaborationTechnical guidancePlanningQuality delivery
Tech Stack:SDCSTATiming closureLECCLPPrelayout STAPostlayout STAEquivalence checkingLintCDCRTLNetlistStatic checksDFTLow powerFisthailExcelliconTCM

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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