Intel

1 week ago

Principal Engineer, AMS IP Architecture

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 5 hours agoStatus: Live

Job Summary

Define and drive next-generation analog and mixed-signal (AMS) IP architectures for Intel products, developing SerDes modeling, calibration, and signal processing algorithms to optimize performance, power, and area. Lead end-to-end PCIe SerDes model architecture in MATLAB/Simulink, run high-speed link simulations for sign-off readiness, correlate models to lab silicon, and partner with analog, digital, and hardware teams to ensure feasible system-level designs.

Location: Santa Clara, Phoenix, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Architecture & Urban Planning

Key Responsibilities

•Architect end-to-end PCIe SerDes (NRZ/PAM4) models in MATLAB/Simulink capturing TX/RX equalization behavior.
•Run 128Gbps+ link simulations to validate protocol specs and reduce margin risk before tapeout.
•Develop real-time calibration/adaptation DSP algorithms balancing convergence speed, stability, and power.
•Validate simulation models against lab silicon measurements and iteratively update behavioral models to close gaps.
•Partner cross-functionally with analog, digital, and hardware teams and provide customer technical support, including link budget analyses and architecture reviews.

Pay and Benefits

Salary: USD 220,920 - 311,890 annually

Equity and Bonus:Equity

Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

•M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field focused on high-speed communications, analog circuits, or signal processing.
•Deep expertise in SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory (equalization, coding, noise filtering).
•Experience analyzing and closing link budgets for NRZ or PAM4 at 100Gbps or higher, including transmitter impairments and receiver noise.
•Hands-on work with SerDes transmitter/receiver architectures and equalization techniques (FFE, DFE, CTLE) or CDR loop dynamics and jitter tolerance.
•Ability to correlate simulation models with silicon measurements, debug discrepancies, and update models to match real-world behavior (C, Verilog-A, or SystemVerilog is a plus).

Education:PhD / Doctorate in Electrical Engineering, Computer Engineering (or related field)

Tech Stack:MATLABSimulinkPCIeNRZPAM4DSPSerDesTXRXEqualizationCalibrationLink simulationTapeoutCVerilog-ASystemVerilogFFEDFECTLECDR

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 week ago

Principal Engineer, AMS IP Architecture

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 5 hours agoStatus: Live

Job Summary

Location: Santa Clara, Phoenix, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Architecture & Urban Planning

Key Responsibilities

•Architect end-to-end PCIe SerDes (NRZ/PAM4) models in MATLAB/Simulink capturing TX/RX equalization behavior.
•Run 128Gbps+ link simulations to validate protocol specs and reduce margin risk before tapeout.
•Develop real-time calibration/adaptation DSP algorithms balancing convergence speed, stability, and power.
•Validate simulation models against lab silicon measurements and iteratively update behavioral models to close gaps.
•Partner cross-functionally with analog, digital, and hardware teams and provide customer technical support, including link budget analyses and architecture reviews.

Pay and Benefits

Salary: USD 220,920 - 311,890 annually

Equity and Bonus:Equity

Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

•M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field focused on high-speed communications, analog circuits, or signal processing.
•Deep expertise in SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory (equalization, coding, noise filtering).
•Experience analyzing and closing link budgets for NRZ or PAM4 at 100Gbps or higher, including transmitter impairments and receiver noise.
•Hands-on work with SerDes transmitter/receiver architectures and equalization techniques (FFE, DFE, CTLE) or CDR loop dynamics and jitter tolerance.
•Ability to correlate simulation models with silicon measurements, debug discrepancies, and update models to match real-world behavior (C, Verilog-A, or SystemVerilog is a plus).

Education:PhD / Doctorate in Electrical Engineering, Computer Engineering (or related field)

Tech Stack:MATLABSimulinkPCIeNRZPAM4DSPSerDesTXRXEqualizationCalibrationLink simulationTapeoutCVerilog-ASystemVerilogFFEDFECTLECDR

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor