Memory Layout Design Engineer

Broadcom
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Communication","Adaptability","Self-reliance","Collaboration","Leadership"]

Design and verify memory layouts for submicron CMOS processes, applying layout guidelines and new process rules to deliver high-quality results on schedule. Manage layout floor-planning, scheduling, and start-to-end deliverables, collaborating with SOC/library teams. Use Cadence layout and verification tools (e.g., Virtuoso, Layout XL, Calibre) and perform physical verification such as LVS/DRC/ERC, antenna, and electromigration checks, with opportunities to support automation and technology reviews.

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FursaFursa
Broadcom
Broadcom
3 days ago

Memory Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 minutes agoStatus: Live
Reposted: similar role first listed 2 weeks ago

Job Summary

Design and verify memory layouts for submicron CMOS processes, applying layout guidelines and new process rules to deliver high-quality results on schedule. Manage layout floor-planning, scheduling, and start-to-end deliverables, collaborating with SOC/library teams. Use Cadence layout and verification tools (e.g., Virtuoso, Layout XL, Calibre) and perform physical verification such as LVS/DRC/ERC, antenna, and electromigration checks, with opportunities to support automation and technology reviews.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Apply layout guidelines, new process rules, and technical requirements to deliver good-quality layouts.
  • •Manage scheduling, timelines, and layout floor-planning to deliver start-to-end results with quality.
  • •Perform memory layout design and physical verification in CMOS processes (LVS/DRC/ERC, antenna, electro-migration).
  • •Plan hierarchy/floor-planning and support chip integration, including memory architecture understanding for signal and power planning.
  • •Adapt to new methodologies and collaborate with the SOC/library team; lead/train junior engineers and support technology reviews and documentation.

Key Requirements

  • •Minimum 3 years of experience with strong layout knowledge.
  • •Bachelor's degree required.
  • •Proficiency using Cadence tools including Virtuoso layout, Layout XL, Cadence schematic capture, and verification tools (CALIBRE, Hercules).
  • •Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).
  • •Experience with digital layout (standard cell, memory, I/O); analog layout experience is a plus.
Experience:3+ years
Education:Bachelor's
Skills:CommunicationAdaptabilitySelf-relianceCollaborationLeadership
Tech Stack:CadenceVirtuosoVirtuoso XLLayout XLCadence schematic captureCALIBREHerculesLVSDRCERCAntennaElectroMigrationFloor-planningHierarchy layoutCMOSSKILL

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn