Intel

2 days ago

Senior Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Own verification planning and execution for interconnect and chassis IP blocks, driving test plans through coverage closure with accountability for quality and schedule. Build scalable, reusable verification environments (testbenches, checkers, constrained-random tests, debug infrastructure), analyze simulation failures, and drive fixes to closure. Collaborate with architecture, design, and software teams on reviews, triage, and spec clarification, and progressively mentor junior engineers while improving automation and regression efficiency.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own verification planning and execution for assigned IP blocks and features from planning through coverage closure with accountability for quality.
•Build scalable verification environments using reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of delivered verification collateral.
•Collaborate with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute beyond DV boundaries to unblock progress.
•Analyze simulation failures, perform root-cause analysis, drive fixes to closure with clear technical communication, and own end-to-end debug for assigned blocks.
•Drive functional coverage planning and coverage closure, continuously improve verification automation and regression efficiency, and mentor junior engineers in verification practices and code quality.

Key Requirements

•5+ years of relevant experience in design verification with IP-level DV and meaningful subsystem-level exposure.
•Strong proficiency in SystemVerilog and UVM methodology.
•Hands-on experience verifying RAS features including error injection, fault propagation, error logging, and recovery sequences.
•Expertise in interconnect and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe, with working knowledge of cache coherency and memory consistency models.
•Solid understanding of SVA (SystemVerilog Assertions) and experience building coverage models and driving test plans to closure.

Experience:5+ years

Education:Bachelor's in Electrical Engineering, Computer Science (or related field)

Skills:MentoringDebuggingTechnical communicationSchedule executionRoot-cause analysis

Tech Stack:SystemVerilogUVMSVAAMBA AXIAMBA ACEAMBA CHIPCIeCXLUCIeLLMRTL/TB code review

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

2 days ago

Senior Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own verification planning and execution for assigned IP blocks and features from planning through coverage closure with accountability for quality.
•Build scalable verification environments using reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of delivered verification collateral.
•Collaborate with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute beyond DV boundaries to unblock progress.
•Analyze simulation failures, perform root-cause analysis, drive fixes to closure with clear technical communication, and own end-to-end debug for assigned blocks.
•Drive functional coverage planning and coverage closure, continuously improve verification automation and regression efficiency, and mentor junior engineers in verification practices and code quality.

Key Requirements

•5+ years of relevant experience in design verification with IP-level DV and meaningful subsystem-level exposure.
•Strong proficiency in SystemVerilog and UVM methodology.
•Hands-on experience verifying RAS features including error injection, fault propagation, error logging, and recovery sequences.
•Expertise in interconnect and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe, with working knowledge of cache coherency and memory consistency models.
•Solid understanding of SVA (SystemVerilog Assertions) and experience building coverage models and driving test plans to closure.

Experience:5+ years

Education:Bachelor's in Electrical Engineering, Computer Science (or related field)

Skills:MentoringDebuggingTechnical communicationSchedule executionRoot-cause analysis

Tech Stack:SystemVerilogUVMSVAAMBA AXIAMBA ACEAMBA CHIPCIeCXLUCIeLLMRTL/TB code review

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor