Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions

Cadence Design Systems
Austin
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 8-12 yearsSkills: ["Customer-facing communication","Cross-functional collaboration","Root-cause analysis","Technical leadership","Influence"]

Lead development and deployment of advanced silicon signoff methodologies for timing, power, signal integrity, and ECO closure. Partner with customers, AE teams, and R&D to debug complex design closure issues, drive STA/MMMC and timing correlation across signoff environments, and support advanced-node tapeouts. Own qualification and certification for advanced-node flows, develop best-practice collateral, and advance adoption of AI-assisted signoff and ECO automation while mentoring engineers and guiding technical reviews.

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Cadence Design Systems
Cadence Design Systems
11 hours ago

Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions

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Last checked: 11 hours agoStatus: Live

Job Summary

Lead development and deployment of advanced silicon signoff methodologies for timing, power, signal integrity, and ECO closure. Partner with customers, AE teams, and R&D to debug complex design closure issues, drive STA/MMMC and timing correlation across signoff environments, and support advanced-node tapeouts. Own qualification and certification for advanced-node flows, develop best-practice collateral, and advance adoption of AI-assisted signoff and ECO automation while mentoring engineers and guiding technical reviews.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Sr. Manager level

Key Responsibilities

  • •Drive development and deployment of advanced signoff methodologies for timing, power, signal integrity, and ECO closure.
  • •Collaborate with customers, AE teams, and R&D to resolve complex design closure challenges and support tapeouts/milestones with root-cause analysis and debug.
  • •Lead qualification and certification for advanced-node design flows and optimize multi-mode multi-corner (MMMC) timing closure methodologies.
  • •Drive signoff correlation across implementation, STA, SPICE, and signoff environments.
  • •Develop deployment collateral, technical presentations, and best-practice methodologies while advancing AI-assisted signoff and ECO automation.

Key Requirements

  • •8-12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.
  • •Strong expertise in Static Timing Analysis (STA) and multi-mode multi-corner (MMMC) timing analysis, including signoff methodology and timing convergence.
  • •Hands-on experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs (including ECO convergence and tapeout).
  • •Proven experience resolving complex technical challenges with semiconductor customers, R&D, and field engineering teams, including root-cause analysis.
  • •Experience leading qualification/certification and independently owning strategic customer engagements with cross-functional execution.
Experience:8-12 yearsSemiconductorsASICSoCEDAAdvanced-node
Skills:Customer-facing communicationCross-functional collaborationRoot-cause analysisTechnical leadershipInfluence
Tech Stack:Static Timing Analysis (STA)Multi-mode multi-corner (MMMC)SPICEECORC extractionParasitic analysisCadence Tempus/PrimeTimeCadence Innovus/ICC/FCTempus ECO/TweakerAI-assisted design closurePower optimizationSignal integrityCrosstalk analysis

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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