Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","Verification environments","Test plans","Memory IP","DDR","HBM","GDDR"]

Lead design verification engineer driving complex design verification efforts with SV/UVM, developing verification environments, test plans, and ensuring closure from concept to verification. Strong SystemVerilog hands-on coding and environment development are essential, with prior IP verification experience (memory IP like DDR/HBM/GDDR) as a plus.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Lead Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Lead design verification engineer driving complex design verification efforts with SV/UVM, developing verification environments, test plans, and ensuring closure from concept to verification. Strong SystemVerilog hands-on coding and environment development are essential, with prior IP verification experience (memory IP like DDR/HBM/GDDR) as a plus.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead design verification for complex designs, driving projects from concept through verification closure.
  • •Develop and maintain verification environments and test plans to ensure robust validation.
  • •Plan and execute environment development, including stimulus, coverage, and debugging strategies.
  • •Collaborate with IP teams and provide technical leadership on memory IP verification (DDR/HBM/GDDR) when applicable.
  • •Mentor junior engineers and contribute to continuous improvement of verification methodologies.

Key Requirements

  • •4+ years of Design Verification experience with SV/UVM.
  • •Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development.
  • •Design verification experience verifying complex designs and leading projects from concept to verification closure.
  • •Strong hands-on UVM and SystemVerilog coding experience and functional verification environment development is required.
  • •Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
Experience:4+ yearsElectronicsVLSIDesign verification
Education:Bachelor's
Skills:SystemVerilogUVMVerification environmentsTest plansMemory IPDDRHBMGDDR
Tech Stack:SystemVerilogUVMSVVerificationDDRHBMGDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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